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? semiconductor components industries, llc, 2006 march, 2006 ? rev. 2 1 publication order number: ncp5006/d ncp5006 compact backlight led boost driver the ncp5006 is a high efficiency boost converter operating in current loop, based on a pfm mode, to drive white led. the current mode regulation allows a uniform brightness of the leds. the chip has been optimized for small ceramic capacitors, capable to supply up to 1.0 w output power. features ? 2.7 to 5.5 v input voltage range ? v out to 24 v output compliance allows up to 5 leds drive in series ? built?in overvoltage protection ? inductor based converter brings up to 90% efficiency ? constant output current regulation ? 0.3 a standby quiescent current ? includes dimming function (pwm) ? enable function driven directly from low battery voltage source ? automatic leds current matching ? thermal shutdown protection ? all pins are fully esd protected ? low emi radiation ? pb?free package is available typical applications ? led display back light control ? keyboard back light ? high efficiency step up converter ncp5006snt1 tsop?5 3000 t ape & ree l tsop?5 sn suffix case 483 pin connections device package shipping ? ordering information ncp5006snt1g tsop?5 (pb?free) 3000 tape & ree l marking diagram 1 5 dcs = device code a = assembly location y = year w = work week = pb?free package 1 5 dcsayw 1 3en v out 2 gnd fb 4 v bat 5 (top view) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification s brochure, brd801 1/d. http://onsemi.com (note: microdot may be in either location)
ncp5006 http://onsemi.com 2 figure 1. typical application gnd u1 en v bat 4 v bat gnd gnd fb ncp5006 5 v bat v out c1 4.7 f gnd 2 3 1 d1 mbr0530 gnd 15 r1 d6 lwt67c d5 lwt67c d4 lwt67c d3 lwt67c d2 lwt67c l1 22 h c2 1.0 f figure 2. block diagram thermal shutdown current sense v sense controller 100 k gnd 4 en 3 fb + ? 300 k +200 mv band gap q1 2 gnd gnd 1 v out 5 v bat v bat
ncp5006 http://onsemi.com 3 pin function description pin pin name type description 1 v out power this pin is the power side of the external inductor and must be connected to the external schottky diode. it provides the output current to the load. since the boost converter operates in a current loop mode, the output voltage can range up to +24 v but shall not extend this limit. however, if the voltage on this pin is higher than the over voltage protection threshold (ovp) the device comes back to shutdown mode. to restart the chip, one must either send a low to high sequence on pin en, or switch off the v bat supply. a capacitor must be used on the output voltage to avoid false triggering of the ovp circuit. this capacitor should be 1.0 f minimum. ceramic type, (esr <100 m ), is mandatory to achieve the high end ef ficiency. this capacitor limits the noise created by the fast transients present in this circuitry. in order to limit the inrush current and to operate with an acceptable start?up time, it is recommended to use any value between 1.0 f and 8.2 f capacitor maximum. care must be observed to avoid emi through the pcb copper tracks connected to this pin. 2 gnd power this pin is the system ground for the ncp5006 and carries both the power and the analog signals. high quality ground must be provided to avoid spikes and/or uncontrolled operation. care must be observed to avoid high?density current flow in a limited pcb copper track. ground plane technique is recommended. 3 fb analog input this pin provides the output current range adjustment by means of a sense resistor connected to the analog control or with a pwm control. the dimming function can be achieved by applying a pwm voltage technique to this pin (see figure 29). the current output tolerance depends upon the accuracy of this resistor. using a 5% metal film resistor or better, yields a good enough output current accuracy. note: a built?in comparator switch off the dc/dc converter if the voltage sensed across this pin and ground is higher than 700 mv (typical). 4 en digital input this is an active?high logic input which enables the boost converter . the built?in pull down resistor disables the device when the en pin is left open. the led brightness can be controlled by applying a pulse width modulated signal to the enable pin (see figure 31). 5 v bat power the external voltage supply is connected to this pin. a high quality reservoir capacitor must be connected across pin 1 and ground to achieve the specified output voltage parameters. a 4.7 f/6.3 v, low esr capacitor must be connected as close as possible across pin 5 and ground pin 2. the x5r or x7r ceramic murata types are recommended. the return side of the external inductor shall be connected to this pin. typical application will use a 22 h, size 1008, to handle the 1.0 to 100 ma max output current range. on the other hand, when the desired output current is above 20 ma, the inductor shall have an esr < 1.5 to achieve a good ef ficiency over the v bat range .
ncp5006 http://onsemi.com 4 maximum ratings rating symbol value unit power supply v bat 6.0 v output power supply voltage compliance v out 28 v digital input v oltage digital input current en ?0.3 < v in < v bat + 0.3 1.0 v ma esd capability (note 1) human body model (hbm) machine model (mm) v esd 2.0 200 kv v tsop?5 package power dissipation @ t a = +85 c (note 2) thermal resistance, junction?to?air p d r ja 160 250 mw c/w operating ambient temperature range t a ?25 to +85 c operating junction temperature range t j ?25 to +125 c maximum junction t emperature t jmax +150 c storage temperature range t stg ?65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114 machine model (mm) 200 v per jedec standard: jesd22?a115 2. the maximum package power dissipation limit must not be exceeded. 3. latch?up current maximum rating: 100 ma per jedec standard: jesd78. 4. moisture sensivity level (msl): 1 per ipc/jedec standard: j?std?020a. power supply section (typical values are referenced to t a = +25 c, min & max values are referenced ?25 c to +85 c ambient temperature, unless otherwise noted.) rating pin symbol min typ max unit power supply 4 v bat 2.7 ? 5.5 v output load voltage compliance 5 v out 21 24 ? v continuous dc current in the load @ v out = 3xled, l = 22 h, esr < 1.5 , v bat = 3.60 v 5 i out 50 ? ? ma stand by current, @ i out = 0 ma, en = l, v bat = 3.6 v 4 i stdb ? 0.3 ? a stand by current, @ i out = 0 ma, en = l, v bat = 5.5 v 4 i stdb ? 0.8 3.0 a inductor discharging time @ v bat = 3.6 v, l = 22 h, 3xled, i out = 10 ma 4 toffmax ? 320 ? ns thermal shutdown protection ? t sd ? 160 ? c thermal shutdown protection hysteresis ? t sdh ? 30 ? c
ncp5006 http://onsemi.com 5 analog section (typical values are referenced to t a = +25 c, min & max values are referenced ?25 c to +85 c ambient temperature, unless otherwise noted.) rating pin symbol min typ max unit high level input v oltage low level input v oltage 4 en 1.3 ? ? ? ? 0.4 v v en pull down resistor 4 r en ? 100 ? k feedback voltage threshold 3 fb 185 200 225 mv output current stabilization time delay following a dc/dc start?up, @ v bat = 3.60 v, l = 22 h, i out = 20 ma 1 i outdly ? 100 ? s internal switch on resistor @ tamb = +25 c 1 qr dson ? 1.7 ? 5. the overall tolerance depends upon the accuracy of the external resistor. esd protection the ncp5006 includes silicon devices to protect the pins against the esd spikes voltages. to cope with the different esd voltages developed in the applications, the built?in structures have been designed to handle 2.0 kv in human body model (hbm) and 200 v in machine model (mm) on each pin. dc/dc operation the dc/dc converter is designed to supply a constant current to the external load, the circuit being powered from a standard battery supply. since the regulation is made by means of a current loop, the output voltage will varies depending upon the dynamic impedance presented by the load. considering high intensity led, the output voltage can range from a low 6.40 v (two led in series biased with a low current), up to 21 v, the voltage compliance the chip can sustain continuously. the basic dc/dc structure is depicted in figure 3. with a 28 v maximum rating voltage capability, the power device can accommodate high voltage source without any leakage current downgrading. por logic control time_out zero_crossing reset gnd vd sense q1 vds l1 22 h v bat d1 c1 d5 d4 d3 d2 gnd vs r2 xr gnd r1 c2 + ? gnd vref v(ipeak) + ? vd sense figure 3. basic dc/dc converter structure 1 3 1.0 f
ncp5006 http://onsemi.com 6 basically, the chip operates with two cycles: cycle #1: time t1, the energy is stored into the inductor cycle #2: time t2, the energy is dumped to the load the por signal sets the flip?flop and the first cycle takes place. when the current hits the peak value, defined by the error amplifier associated to the loop regulation, the flip?flop resets, the nmos is deactivated and the current is dumped into the load. since the timings depend on the environment, the internal timer limits the toff cycle to 320 ns (typical), making sure the system operates in a continuous mode to maximize the energy transfer. figure 4. basic dc?dc operation first start?up normal operation i l 0 ma ids 0 ma io 0 ma iv ipeak t t t t1 t2 based on the data sheet, the current flowing into the inductor is bounded by two limits: ? ipeak value: internally fixed to 350 ma typical ? iv value: limited by the fixed toff time built in the chip (320 ns typical) the system operates in a continuous mode as depicted in figure 4 and t 1 and t 2 times can be derived from basic equations. (note: the equations are for theoretical analysis only, they do not include the losses.) l e* di dt (eq. 1) let v bat = e, then: t1 (ip iv) * l v bat (eq. 2) t2 (ip iv) * l vo v bat (eq. 3) since t 2 = 320 ns typical and vo = 21 v maximum, then (assuming a typical v bat = 3.0 v): i t2 * (vo v bat) l (eq. 4) imax 320 ns * (21?3.0) 22 h 261 ma of course, from a practical stand point, the inductor must be sized to cope with the peak current present in the circuit to avoid saturation of the core. on top of that, the ferrite material shall be capable to operate at high frequency (1.0 mhz) to minimize the foucault?s losses developed during the cycles. the operating frequency can be derived from the electrical parameters. let v = vo ? v bat , rearranging equation 1: ton di * l e (eq. 5) since toff is nearly constant (according to the 320 ns typical time), the di is constant for a given load and inductance value. rearranging equation 5 yields: ton v*dt l *l e (eq. 6) let e = v bat , and vopk = output peak voltage, then: ton (vopk v bat )*dt v bat (eq. 7) finally, the operating frequency is: f 1 ton toff (eq. 8) the output power supplied by the ncp5006 is limited to one watt: figure 5 shows the maximum power that can be delivered by the chip as a function of the output voltage.
ncp5006 http://onsemi.com 7 1200 6 400 5 3 p out (mw) 0 v bat (v) 200 800 1000 600 24 p out = f(v bat ) @ r sense = 2.0 4 led 120 40 i out (ma) 0 v bat (v) 20 80 100 60 3.0 4.0 5.0 2.5 3.5 4.5 5.5 figure 5. maximum output power as a function of the battery supply voltage figure 6. typical inductor peak current as a function of v bat voltage figure 7. maximum output current as a function of v bat 350 4 3 2 ipeak (ma) 150 400 v bat (v) 200 300 5 250 6 test conditions: l = 22 h, r sense = 10 , tamb = +20 c test conditions: l = 22 h, r sense = 2.0 , tamb = +25 c 2 led 3 led 4 led 5 led p out = f(v bat ) @ rs = 2.0 i peak = f(v bat ) @ l out = 22 h 3 led 2 led 5 led
ncp5006 http://onsemi.com 8 output current range set?up the current regulation is achieved by means of an external sense resistor connected in series with the led string. controller gnd 3 fb gnd 1 v out d1 load q1 figure 8. output current feedback v bat l1 22 h r1 x the current flowing through the led creates a voltage drop across the sense resistor r1. the voltage drop is constantly monitored internally, and maximum peak current allowed in the inductor is set accordingly in order to keep constant this voltage drop (and thus the current flowing through the led). for example, should one need a 10 ma output current, the sense resistor should be sized according to the following equation: r 1 feedback threshold i out 200 mv 10 ma 20 (eq. 9) a standard 5% tolerance resistor, 22 smd device, yields 9.09 ma, good enough to fulfill the back light demand. the typical application schematic diagram is provided in figure 9. figure 9. basic schematic diagram gnd en 2 1 5 v out v bat ncp5006 l1 22 h v bat c1 4.7 f gnd d6 d5 d4 d3 u1 4 d2 gnd 3 gnd r1 22 d1 mbr0530 gnd c2 1.0 f fb pulse lwt67c lwt67c lwt67c lwt67c lwt67c
ncp5006 http://onsemi.com 9 output load drive in order to optimize the built?in boost capabilities, one shall operate the ncp5006 in the continuous output current mode. such a mode is achieved by using and external reservoir capacitor (see table 1) across the led. at this point, the peak current flowing into the led diodes shall be within the maximum ratings specified for these devices. of course, pulsed operation can be achieved, due to the en signal pin 4, to force high current into the led when necessary. the schottky diode d1, associated with capacitor c2 (see figure 9), provides a rectification and filtering function. when a pulse?operating mode is acceptable: ? a pwm mode control can be used to adjust the output current range by means of a resistor and a capacitor connected across fb pin. on the other hand, the schottky diode can be removed and replaced by at least one led diode, keeping in mind such led shall sustain the large pulsed peak current during the operation. typical operating characteristics 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 yield (%) 5 led/10 ma 3 led/10 ma 4 led/10 ma 2 led/10 ma 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 yield (%) 5 led/4 ma 3 led/4 ma 4 led/4 ma 2 led/4 ma figure 10. overall efficiency vs. power supply @ i out = 4.0 ma, l = 22 h figure 11. overall efficiency vs. power supply @ i out = 10 ma, l = 22 h 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 vbat (v) yield (%) 5 led/20 ma 3 led/20 ma 4 led/20 ma 2 led/20 ma 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 vbat (v) yield (%) 5 led/15 ma 3 led/15 ma 4 led/15 ma 2 led/15 ma figure 12. overall efficiency vs. power supply @ i out = 15 ma, l = 22 h figure 13. overall efficiency vs. power supply @ i out = 20 ma, l = 22 h yield = f(v bat ) @ i out = 4.0 ma/l out = 22 h yield = f(v bat ) @ i out = 10 ma/l out = 22 h yield = f(v bat ) @ i out = 15 ma/l out = 22 h yield = f(v bat ) @ i out = 20 ma/l out = 22 h v bat (v) v bat (v)
ncp5006 http://onsemi.com 10 figure 14. overall efficiency vs. power supply @ i out = 40 ma, l = 22 h figure 15. feedback voltage stability yield (%) v bat (v) 205 200 feedback voltage (mv) 195 temperature ( c) 199 202 203 201 020 10 0 198 197 196 ?40 40 ?20 60 80 204 5 0 feedback varia tion (%) ?5 temperature ( c) ?1 2 3 1 0 20 100 ?2 ?3 ?4 ?40 40 ?20 60 80 4 v bat = 3.1 v thru 5.5 v v bat = 3.1 v thru 5.5 v figure 16. feedback voltage variation 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 5 led/40 ma 3 led/40 ma 4 led/40 ma 2 led/40 ma feedback variation vs. temperature feedback v ariation vs. nominal (v bat = 3.0 v, 6.0 v, t = 25 c) figure 17. standby current 1.4 2.7 istby ( a) 0.0 v bat (v) 0.6 1.0 0.8 5 .5 0.4 0.2 1.2 ?40 c thru 125 c 3.3 3.9 4.5 5.1 standby current vs. v bat 4 led 5 led figure 18. typical operating frequency 0 0.5 1.0 1.5 2.0 2.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2 led f (mhz) v bat (v) 3 led figure 19. overvoltage protection 26 24 ?40 overvoltage protection (v) 22 temperature ( c) 25 0 100 23 40 80 v bat = 5.5 v v bat = 2.7 v v bat = 3.6 v 20 13 0 ?20 60 120 frequency = f(v bat ) @ i out = 20 ma?l out = 22 h ovp vs. temperature yield = f(v bat ) @ i out = 40 ma/l out = 22 h all curve conditions: l = 22 h, c in = 4.7 f, c out = 1.0 f, typical curve @ t = +25 c
ncp5006 http://onsemi.com 11 figure 20. typical power up response figure 21. typical start?up inductor current and output voltage typical operating waveforms conditions: v bat = 3.6 v, l out = 22 h, 5 led, i out = 15 ma conditions: v bat = 3.6 v, l out = 22 h, 5 led, i out = 15 ma inductor current v out v out inductor current
ncp5006 http://onsemi.com 12 figure 22. typical inductor current figure 23. typical output voltage ripple typical operating waveforms conditions: v bat = 3.6 v, l out = 22 h, 5 led, i out = 15 ma conditions: v bat = 3.6 v, l out = 22 h, 5 led, i out = 15 ma inductor current inductor current v out ripple 50 mv/div
ncp5006 http://onsemi.com 13 figure 24. typical output peak voltage typical operating waveforms test conditions: l = 22 h, i out = 15 ma, v bat = 3.6 v, ambient t emperature output voltage inductor current figure 25. efficiency as a function of v bat and inductor esr 78.00 80.00 82.00 84.00 86.00 88.00 90.00 92.00 3 3.5 4 4.5 5 5.5 v bat (v) efficiency (%) esr = 1.3 esr = 0.3 ncp5006: efficiency = f(esr) @ 5 led, iled = 20 ma
ncp5006 http://onsemi.com 14 figure 26. noise returned to the battery test conditions: v bat = 3.6 v, i out = 20 ma, string of 3 led (osram lwt67c) figure 27. relative emi over 100 khz ? 30 mhz bandwidth 10.00 1.00 0.10 0.01 1000 100 10 1 0.1 frequency (mhz) noise ( v/sqr/hz)
ncp5006 http://onsemi.com 15 typical applications circuits standard feedback the standard feedback provides a constant current to the led, independently of the v bat supply and number of led associated in series. figure 28 depicts a typical application to supply 13 ma to the load. figure 28. basic dc current mode operation with analog feedback en 1 5 v out v bat r1 ncp5006 l1 22 h v bat c1 4.7 f d6 d5 d4 d3 u1 4 d2 v bat 2 gnd gnd fb 3 d1 mbr0530 15 gnd gnd c2 1.0 f lwt67c gnd lwt67c lwt67c lwt67c lwt67c pwm operation the analog feedback pin 3 provides a way to dim the led by means of an external pwm signal as depicted in figure 29. by optimizing the internal high impedance presented by the fb pin, one can set up a simple r/c network to accommodate such a dimming function. two modes of operation can be considered: ? pulsed mode, with no filtering ? averaged mode with filtering capacitor although the pulsed mode will provide a good dimming function, from a human eye standpoint, it will continuously start and stop the converter, yielding high transients . these transients might generate spikes dif ficult to filter out in the rest of the application, a situation not recommended. the output current depends upon the duty cycle of the signal presented to the node pin 3: this is very similar to the digital control discussed in figure 31. the average mode yields a noise free operation since the converter operates continuously , together with a very good dimming function. the cost is an extra resistor and one extra capacitor, both being low cost parts.
ncp5006 http://onsemi.com 16 figure 29. basic dc current mode operation with pwm control en 1 5 v out v bat r1 ncp5006 l1 22 h v bat c1 4.7 f u1 4 v bat 2 gnd gnd fb 3 d1 mbr0530 10 gnd gnd c2 1.0 f r4 5.6 k r3 10 k gnd c3 100 nf sense resistor r2 150 k pwm average network note: rc filter r2 and c3 is optional (see text) gnd d6 d5 d4 d3 d2 lwt67c lwt67c lwt67c lwt67c lwt67c to implement such a function, let consider the feedback input as an operational amplifier with a high impedance input (reference schematic figure 29). the analog loop will keep going to balance the current flowing through the sense resistor r1 until the feedback voltage is 200 mv. an extra resistor (r4) isolates the fb node from low resistance to ground, making possible to add an external voltage to this pin. the time constant r2/c3 generates the voltage across c3, added to the node pin 1, while r2/r3/r4/r1/c3 create the discharge time constant. in order to minimize the pick up noise at fb node, the resistors shall have relative medium value, preferably well below 1.0 m . consequently, let r2 = 150 k, r3 = 10 k and r4 = 5.6 k. on the other hand, the feedback delay to control the luminosity of the led shall be acceptable by the user, 10 ms or less being a good compromise. the time constant can now be calculated based on a 400 mv offset voltage at the c3/r2/r3 node to force zero current to the led. assuming the pwm signal comes from a standard gate powered by a 3.0 v supply, running at 10 khz, then a full dimming of the led can be achieved with a 95% span of the duty cycle signal. figure 30 depicts the behavior under such pwm analog mode. figure 30. operation with analog pwm, f = 10 khz, dc = 25% pwm vfb vpwm
ncp5006 http://onsemi.com 17 digital control due to the en pin, a digitally controlled luminosity can be implemented by providing a pwm signal to this pin (see figure 31). the output current depends upon the duty cycle, but care must be observed as the dc/dc converter is continuously pulsed on/off and noise are likely to be generated. figure 31. typical semi?pulsed mode of operation en 1 5 v out v bat r1 ncp5006 l1 22 h v bat c1 4.7 f gnd u1 4 2 gnd gnd fb 3 d1 mbr0530 22 gnd gnd pulse c2 1.0 f note: pulse width and frequency depends upon the application constraints. d6 d5 d4 d3 d2 lwt67c lwt67c lwt67c lwt67c lwt67c the pwm operation, using the en pin as a digital control, is depicted in figures 32 and 33. the tests have been carried out at room temperature with v bat = 3.60 v, l = 22 h, five leds in series, rfb = 22 . pwm vfb vpwm v out figure 32. operation @ pwm = 10 khz, dc = 10%
ncp5006 http://onsemi.com 18 pwm vfb pwr clk v out figure 33. operation @ pwm = 10 khz, dc = 25% pwm pwr clk v out figure 34. magnified view of operation @ pwm = 10 khz, dc = 25%
ncp5006 http://onsemi.com 19 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 0 20 40 60 80 100 120 dc (%) figure 35. output current as a function of the operating condition i out (ma) digital en analog pwm ncp5006 i out = f(pwm) @ f = 10 khz table 1. recommended passive parts part manufacturer description part number ceramic capacitor 1.0 f/16 v murata grm42 ? x7r grm42?6x7r?105k16 ceramic capacitor 1.0 f/25 v murata grm42 ? x5r grm ceramic capacitor 4.7 f/6.3 v murata grm40 ? x5r grm40?x5r?475k6.3 inductor 22 h coilcraft 1008ps ? shielded 1008ps?223mc inductor 22 h coilcraft power w afer lpq4812?223kxc inductor 22 h wurth power choke 744031220 inductor 22 h tdk power inductor vlp4614t?220mr40
ncp5006 http://onsemi.com 20 typical leds load mapping since the output power is voltage battery limited (see figure 5), one shall arrange the led to cope with a specific need. in particular, since the power cannot extend 600 mw under realistic battery supply, powering ten led can be achieved by a series/parallel combination as depicted in figure 36. figure 36. examples of possible led arrangements d1 led d2 led d3 led d4 led d5 led d6 led d7 led d8 led d9 led d10 led load 75 ma 7.0 v (typ.) d1 led d2 led d3 led d4 led load 50 ma 14 v (typ.) d1 led d2 led load 60 ma 10.5 v (t yp.) d3 led d4 led d5 led d6 led d7 led d8 led d9 led d5 led d6 led d7 led d8 led d10 led d11 led d12 led d13 led d14 led d15 led gnd r1 3.9 sense resistor test conditions: v bat = 3.6 v l out = 22 h c out = 1.0 f gnd r1 2.7 sense resistor gnd r1 3.3 sense resistor
ncp5006 http://onsemi.com 21 figure 37. ncp5006 demo board schematic diagram gnd c2 4.7 f/ 16 v c3 4.7 f/ 16 v tp? v out lwt67c d9 lwt67c d10 lwt67c d11 lwt67c d6 lwt67c d7 lwt67c d8 lwt67c d5 lwt67c d12 mmbf0201nlt1 r7 3.3 r q2 gnd q1 r6 51 r mmbf0201nlt1 rccom ctc tra trb clr u4a m54hc123 q q 13 4 15 14 1 2 3 v cc gnd u5 1 6 4 5 nlas4599 v out tp1 vfb u1 v out fb gnd d2 mbr0530 l1 22 h 4 gnd 1 2 v bat 5 en 3 ncp5006 c9 1.0 f/ 10 v gnd r4 10 k 500 ka p2 v cc adjust flash pulse width 4.7 f/6.0 v c1 gnd 8 u2c hc132 10 9 gnd 1n4148 d4 v cc 10 k r1 10 k r2 c7 1.0 nf 1n4148 d3 v cc 11 u2d 12 13 snj54hc132 c8 10 f/ 10 v 11 u2d 12 13 hc132 6 u2b 4 5 snj54hc132 hc132 r3 10 k p1 100 ka adjust flash duty cycle 3 u2a 1 2 snj54hc132 hc132 r5 100 k s1 gnd trig 1 2 3 v cc gnd gnd gnd 1 2 j1 enable j2 v bat d1 mbr0530 v cc c4 4.7 f/ 16 v c5 100 nf c6 100 nf gnd d13 repeat r8 1.5 k gnd v cc s2 single/repeat
ncp5006 http://onsemi.com 22 figure 38. ncp5006 demo board pcb: top layer figure 39. ncp5006 demo board pcb: bottom layer figure 40. ncp5006 demo board top silkscreen
ncp5006 http://onsemi.com 23 figures index figure 1: typical application 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 2: block diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 3: basic dc/dc converter structure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 4: basic dc/dc operation 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 5: maximum output power as a function of the battery supply voltage 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 6: typical inductor peak current as a function of v bat voltage 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 7: maximum output current as a function of v bat 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 8: output current feedback 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 9: basic schematic diagram 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 10: overall efficiency vs. power supply @ i out = 4.0 ma, l = 22 h9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 11: overall efficiency vs. power supply @ i out = 10 ma, l = 22 h9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 12: overall efficiency vs. power supply @ i out = 15 ma, l = 22 h9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 13: overall efficiency vs. power supply @ i out = 20 ma, l = 22 h9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 14: overall efficiency vs. power supply @ i out = 40 ma, l = 22 h10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 15: feedback voltage stability 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 16: feedback voltage variation 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 17: standby current 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 18: typical operating frequency 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 19: overvoltage protection 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 20: typical power up response 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 21: typical start?up inductor current and output voltage 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 22: typical inductor current 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 23: typical output voltage ripple 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 24: typical output peak voltage 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 25: efficiency as a function of v bat and inductor esr 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 26: noise returned to the battery 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 27: relative emi over 100 khz?30 mhz bandwidth 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 28: basic dc current mode operation with analog feedback 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 29: basic dc current mode operation with pwm control 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 30: operation with analog pwm, f = 10 khz, dc = 25% 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 31: typical semi?pulsed mode of operation 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 32: operation @ pwm = 10 khz, dc = 10% 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 33: operation @ pwm = 10 khz, dc = 25% 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 34: magnified view of operation @ pwm = 10 khz, dc = 25% 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 35: output current as a function of the operating conditions 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 36: examples of possible led arrangements 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 37: ncp5006 demo board schematic diagram 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 38: ncp5006 demo board pcb: top layer 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 39: ncp5006 demo board pcb: bottom layer 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 40: ncp5006 demo board top silkscreen 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note captions index note 1: this device series contains esd protection and exceeds the following tests 4 . . . . . . . . . . . . . . . . . . . . . . . . . note 2: the maximum package power dissipation limit must not be exceeded 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 3: latch?up current maximum rating: 100 ma per jedec standard: jesd78 4 . . . . . . . . . . . . . . . . . . . . . . . . note 4: moisture sensivity level (msl): 1 per ipc/jedec standard: j?std?020a 4 . . . . . . . . . . . . . . . . . . . . . . . . note 5: the overall tolerance depends upon the accuracy of the external resistor 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . abbreviations en enable fb feed back por power on reset: internal pulse to reset the chip when the power supply is applied
ncp5006 http://onsemi.com 24 package dimensions tsop?5 sn suffix case 483?02 issue c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. a and b dimensions do not include mold flash, protrusions, or gate burrs. dim min max min max inches millimeters a 2.90 3.10 0.1142 0.1220 b 1.30 1.70 0.0512 0.0669 c 0.90 1.10 0.0354 0.0433 d 0.25 0.50 0.0098 0.0197 g 0.85 1.05 0.0335 0.0413 h 0.013 0.100 0.0005 0.0040 j 0.10 0.26 0.0040 0.0102 k 0.20 0.60 0.0079 0.0236 l 1.25 1.55 0.0493 0.0610 m 0 10 0 10 s 2.50 3.00 0.0985 0.1181 0.05 (0.002) 123 54 s a g l b d h c k m j __ _ _ 0.7 0.028 1.0 0.039 mm inches scale 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp5006/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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